New Validation and Test Problems for High Performance Deep Sub- Micron VLSI Circuits Presenters:

This tutorial will focus on the emergence of new validation and test issues, factors motivating the emergence of these problems, basic models and the analysis of the underlying electrical phenomena, and several case studies. The primary factors causing a paradigm shift in the area of validation and test that will be discussed are deep sub-micron CMOS technology, high performance system architecture, short rise/fall times of signals, and variations in electrical parameter values due to process variations. These factors influence R, L, C, dI/dt, and dV/dt values, which in turn impact ground bounce, crosstalk, and clock skew, which in turn impact performance. In the area of crosstalk, we will discuss the phenomena of unwanted pulses, data dependent circuit behavior, and how coupling affects signal transition time. We will also show the effect of variations in electrical parameters on circuit “noise” and illustrate how this noise can induce erroneous circuit operation in a large variety of circuits, such as dynamic logic and Vt sensitive circuits. The need to develop new design corners will be discussed as well. Ways of addressing these problems at the design, validation, and test phases of a project will be described along with several illustrative case studies.